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Scientists shrink fin-width of FinFET to nearly the physical limit

wallpapers News 2021-01-10
Different configurations of MOSFET.

FinFETs are known to be an evolution of metal-oxide-semiconductor field effect transistors (MOSFETs) featuring a semiconducting channel vertically wrapped by conformal gate electrodes. It was first proposed in 1990s in order to avoid the short channel effect and other drawbacks resulted from the shrinking of transistor size. Because of the limitation of nanofabrication, the minimum fin width is about 5 nm in current technology.

In the past decades, microelectronics has developed in a rapid pace following the Moore's Law, with the number of transistors per area increased bi-yearly. Due to the limitation of nano-fabrication precision, it is now extremely challenging to shrink further the size of transistors on an integrated circuit. It is therefore of great importance to seek new candidates of semiconducting materials.

In recent years, novel materials such as carbon nanotubes and two dimensional (2-D) materials have been widely studied for the implementation of nano-scaled transistors. In a new study published in Nature Communications, the researchers from the Institute of Metal Research (IMR) of the Chinese Academy of Sciences and France aimed at replacing the conventional Si-based fin with 2-D single atomic layer in the FinFET architecture.

The researchers designed a wet-sprayed chemical vapor deposition (CVD) method to universally grow monolayers of transition metal dichalcogenides (ML-TMDCs, such as MoS2 and WS2) on step-shaped templates with height at the order of 300 nm.

After a dedicated work flow of multiple-step etching and nano fabrication processes, vertically standing single layer MoS2 channels are successfully wrapped with dielectric and gate electrodes, with source and drain electrodes contacting the 0.6 nm fin channel. Gate electrodes can also be made of a carbon nanotube thin film.

The best electrical performances of such ML-FinFETs were obtained to show on/off ratio reaching 107, sub-threshold swing of about 300 mV/dec, and mobilities at the order of a few cm2V-1s-1. Simulations showed that by further optimizing the structure of the ML-FinFETs, drain-induced-barrier-lowering (DIBL) can be lowered to 5 mV/V.

This study achieved a FinFET with sub 1 nm fin width via a bottom-up route to grow monolayered (ML) MoS2 (thickness ~ 0.6 nm) as the fin, which is nearly the physical limit that one can actually achieve. Fin-arrays with minimum pitch of 50 nm are also demonstrated, providing new insights for the implementation of nanoelectronics in the foreseeable future where the Moore's Law might be no longer valid.

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